1. Field of the Invention
The present invention relates to a semiconductor device, and can, for example, be applied to a semiconductor device with a multi-layer wiring configuration comprising a pad part, a plurality of interlayer insulation films and wiring arranged in the interlayer insulation films.
2. Description of the Background Art
There exists a semiconductor device where a plurality of layers of interlayer insulation films are stacked on a semiconductor substrate and a pad part is placed on the top layer of the interlayer insulation films. Here, multi-layer wiring and vias for connecting each of the wiring are formed in the interlayer insulation films.
Further, with advancement of micro-fabrication of the semiconductor device having the above-mentioned configuration, a bonding pad of the device has been reduced in size. Moreover, there has posed a problem of signal delay due to the micro-fabrication. From the view point of preventing the signal delay and the like, an insulation layer with a lower dielectric constant than that of a silicon oxide has been applied as the interlayer insulation film. Here, generally, a porous insulation film is often applied as the insulation film with a low dielectric constant.
However, the above-mentioned insulation film with a low dielectric constant has relatively small strength. Therefore, when the insulation film with a low dielectric constant is applied, cracking might occur in the insulation film with a low dielectric constant at the time of bonding with respect to the pad part. Further, the insulation film with a low dielectric constant typically has unfavorable adhesiveness to other members. Hence, when the insulation film with a low dielectric constant is applied, film-peeling might occur on the upper face (or lower face) of the insulation film with a low dielectric constant at the time of probing with respect to the pad part.
As a technique for suppressing occurrence of cracking and film-peeling, for example, Japanese Patent Application Laid-Open No. 2001-267323 is cited.
In the technique according to Japanese Patent Application Laid-Open No. 2001-267323, a dummy pattern was formed in every layer of the insulation films with a low dielectric constant under the pad part. Here, in Japanese Patent Application Laid-Open No. 2001-267323, the dummy pattern is formed in each of the insulation films having smaller mechanical strength and lower dielectric constant (e.g., insulation films with a dielectric constant k of less than 4) than those of silicon oxide film. Here, generally, a porous insulation film is often applied as the insulation film with a low dielectric constant.
As thus described, in Japanese Patent Application Laid-Open No. 2001-267323, the dummy pattern is formed in each of the insulation films having smaller mechanical strength and lower dielectric constant (e.g., insulation films with a dielectric constant k of less than 4) than those of silicon oxide film.
Accordingly, regions for forming wiring and the like which function as elemental devices are reduced. Further, there has occurred a problem in that the production process becomes complex to increase production cost.